The present invention relates to an information processing device, especially an information processing device enabling to freely set a breakpoint.
Conventionally, there has been a method using a pipeline structure as one of means for improving performance of the information processing device.
The inside of this information processing device with the pipeline structure is divided into some functionally independent units that operate in parallel.
An explanation of the information processing device having such a pipeline structure is done in the lines that follow.
FIG. 5 is a block diagram of an information processing device 40 having the pipeline structure.
A bus control unit 41 in this figure is a unit exchanging data with external memories and peripheral devices of the information processing device 40.
A prefetch unit 42 is a unit for controlling to fetch instruction codes and for storing the fetched instructions into a buffer in the prefetch unit 42.
An instruction decoding unit 43 reads out the instructions stored in the buffer of the prefetch unit 42 in order and decodes them into a data format for an execution unit 44.
The execution unit 44 is a unit for executing the instructions in accordance with the decoded instructions.
For debugging a program with an in-circuit emulator, one of these information processing device, there is a method using breakpoints.
Next, the breakpoints are explained.
A user who intends to debug a user program sets in advance some addresses (breakpoints) that suspend program in the user program during execution of a monitor program of the in-circuit emulator.
Consecutively, during executing the user program, the breakpoint detection circuit detects an address that suspends execution of the user program and generates an interrupt before or after execution of an instruction that is set with the breakpoint.
Then, the control of the instruction is moved to the monitor program. The user can operate the monitor program to display the contents of a register or a memory to debug the user program.
As an art that realizes such a break in an information processing device having a pipeline structure, there is an art described in the Japanese Patent Laid-Open No.175539 (1993).
FIG. 6 is a block diagram showing a flow of a break operation of the above-mentioned art.
When the bus control unit 41 fetches an instruction from a data bus 46 and the address of the instruction to be executed and that of a breakpoint coincide, the breakpoint detection circuit 50 makes an external break signal A active. Information of the external break signal A is taken into the prefetch unit 42 with the fetched instruction B.
Then, the information of the external break signal A is brought to the execution unit 44 with the fetched information.
Next, movement of the information to the execution unit 44 from the instruction decoding unit 43 is explained using FIG. 7 showing a typical example.
A buffer 61 having information of a decoded instruction C and the external break signal A exists in the instruction decoding unit 43. The information is sent into both an instruction execution processing section 51 and an interrupt control section 52 in the execution unit 44.
Also, the instruction decoding unit 43 makes an instruction input signal D active when sending out the information of the decoded instruction C and the external break signal A to the execution unit 44. In addition, the instruction input signal D is also sent into the interrupt control section 52.
Consecutively, an internal operation of the execution unit 44 is explained in the following three cases.
(1) The case that a breakpoint is set in the first byte of an instruction code and a selector outputs an interrupt signal for debugging before execution of the instruction code. PA0 (2) The case that a breakpoint is set in the first byte of an instruction code and a selector outputs an interrupt signal for debugging after execution of the instruction code. PA0 (3) The case that a breakpoint is set in or after the second byte of an instruction code.
When the first byte of the decoded instruction C in which the breakpoint is set has been input into the instruction execution processing section 51, the external break signal A that has been made active by the breakpoint detection circuit 50 is input into a delay-flip-flop 53 (delay-flip-flop is shortened as D-F/F in figures) in the interrupt control section 52.
Moreover, the instruction input signal D that informs the moment just before execution of the instruction code is output to the delay-flip-flop 53 by the instruction decoding unit 43.
Then, the interrupt signal for before-execution of instruction E that is an output signal of the delay-flip-flop 53 becomes active.
Next, When an instruction execution completion signal F that is output at the time of completion of an instruction execution taken by the instruction execution processing section 51 has been output, an interrupt signal for after-execution of instruction G that is an output of the delay-flip-flop 54 becomes active.
And, the outputs of the delay-flip-flops 53 and 54 are input into the selector 55 as an input X and an input Y, respectively.
Here, the selector 55 generates an interrupt signal I for debugging at the time of input of said interrupt signal for before-execution of instruction E, that is, the time before execution of the instruction, because the before-execution of an instruction (the input X of the selector 55) is selected as an output for interrupt for debugging by a selection signal H from the register 56.
The interrupt processing section 57 receives the interrupt signal for debugging I at a sampling timing, suspends the following instructions and moves execution onto the other address. An operation timing at this time is shown in FIG. 8.
The operation to the point that the outputs of the delay-flip-flops 53 and 54 are input into the selector 55 is the same as the case of the above-mentioned (1), so explanation is omitted.
The selector 55 generates the interrupt signal for debugging I at the time of input of said interrupt signal for after-execution of instruction G, that is, the time after execution of the instruction, because the after-execution of instruction (the input Y of the selector 55) is selected as an output for interrupt for debugging by the selection signal H from the register 56.
Then, similarly to the case (1), the interrupt processing section 57 receives an interrupt. The operation timing at this time is shown in FIG. 9.
When the byte of the decoded instruction C in which the breakpoint is set has been input into the execution processing section 51, the external break signal A that has been made active by the breakpoint detection circuit 50 is input into the delay-flip-flop 53 in the interrupt control section 52.
At this time, the instruction input signal D is not output in or after the second byte of the decoded instruction C, because the instruction input signal D has been output in synchronized with the first byte of the decoded instruction C.
Therefore, when a breakpoint is set in or after the second byte of the decoded instruction C, the instruction input signal D is not output in synchronized with the external break signal A.
As a result, the interrupt signal for before-execution of instruction E is not output because the delay-flip-flop 53 neglects the external break signal A.
In addition, also the delay-flip-flop 54 uses the interrupt signal E for before-execution of instruction as an input, so it cannot output the interrupt signal for after-execution of instruction G.
Therefore, also the interrupt signal for debugging I is not output.
The operation timing at this time is shown in FIG. 10. (The case that a breakpoint is set in the second byte of the instruction code is shown).
Like this, in the case that a breakpoint is set in or after the second byte of an instruction code, an interrupt signal for debugging is not output and interrupt processing is neglected because the instruction input signal D is not output at the time of occurrence of the external break signal A.
For this reason, the prior art has a limitation that user must set a breakpoint at the user first byte of an instruction.